FIG. 1 is a block diagram of a portion of a conventional FPGA 100. The FPGA 100 typically includes a two dimensional. array of configurable logic blocks (CLBs), which includes CLBs 101A-101I as illustrated. Each of these CLBs 101A-101I includes a block of configurable logic elements (CLEs) and corresponding programmable routing resources. For example, CLB 101A includes CLE 102 and routing resources 103. The routing resources associated with the various CLBs can be programmed by the user to provide various connections among the CLEs. In addition, the user can program the CLEs to implement different functions.
The flexibility provided by CLBs 101A-101I comes at the cost of logic density. For example, suppose that the CLBs 101A-101E are configured to implement an adder function having a certain number of bits. The CLBs required to implement such an adder function will have a larger layout area than a dedicated adder function having the same number of bits. FPGA 100 exhibits a reduced logic density with respect to dedicated circuits because of the additional resources required to make the routing resources and the CLEs programmable.
As an alternative to FPGAS, non-field programmable gate arrays can be programmed to implement application specific functions. The function of a non-field programmable gate array is defined during the later stages of manufacture, after a defined pattern of transistors has been formed. (A field programmable gate array, as its name implies, is programmed by the user.) An example of a non-field programmable gate array is a sea-of-gates (SOG) gate array, which is a mask programmed gate array.
An SOG gate array, in which a pattern of transistors are interconnected by custom patterns of metal lines, has a significantly higher logic density than the CLBs 101A-101I of FPGA 100. In an SOG gate array, a predefined pattern of transistors are connected directly with user-defined metal, both to form gates and to interconnect those gates. Consequently, the extensive programmable routing resources required for FPGA 100 are not present in an SOG gate array. However, non-field programmable gate arrays, such as SOG gate arrays, are inflexible in that they do not provide for field programmability.
FPGAs and non-field programmable gate arrays have been combined in a single device as set forth by Tavana et al. in U.S. patent application Ser. No. 08/721,392 filed Sep. 26, 1996, now issued as U.S. Pat. No. 5,825,202. However, this patent describes an FPGA portion of the device which is located within one dedicated region, and a non-field programmable gate array portion of the device which is located within a separate dedicated region. These dedicated regions are laterally separated, such that a common boundary separates the FPGA portion from the non-field programmable gate array portion. As a result of this layout, all interconnections between the FPGA portion and the non-field programmable gate array portion must cross the common boundary. This requirement can result in interconnect congestion, which in turn, can result in interconnect routing limitations.
It would therefore be desirable to have an FPGA which exhibits the field programmability of a conventional FPGA, as well as the improved logic density of a non-field programmable gate array, without exhibiting excessive congestion within the interconnect structure.